WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance
THE ROLE:
Push Boundaries, Deliver Innovation and Change the World! In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Gaming Consoles, Servers and Personal Computers as well as Graphics Cards and VR sets. This team also is responsible for the Design and Verification of several critical as well as the integration to other subsystems and SOC. The Design and Design Verification groups within this team are also responsible for developing a balanced architecture between power consumption and performance, delivering high complexity RTL code and creating advanced testbenches using cutting edge verification techniques.
KEY RESPONSIBILITIES:
Develop RTL code for high-speed IO controller blocks in Verilog HDL and make sure functional correct and reusable for different configuration.
Work in synthesis and netlist delivery that meets timing, area and power bounding box. Assist physical design team on the floor-planning and timing closure.
Work with Design Verification team to ensure quality for architecture definition and design implementation.
PREFERRED EXPERIENCE:
Over 3 years of digital IP/SoC development
Good working experience in computer architecture and interconnects.
Good working experience in full ASIC design cycle: requirements definition, architectural and micro-architectural specification, RTL, design verification, floor-planning, synthesis, timing closure, post-silicon validation
Good command of Verilog RTL design and has experience of large digital ASIC project.
Familiarity in high-speed IO controller design (e.g. USB, Thunderbolt, UFS) is a plus.
Working experience in with front-end EDA tools and flows.
Working experience with Unix/Linux and scripts (tcl, perl, ruby and etc.)
Excellent interpersonal, communication, and writing skills. Able to provide clear and logical presentations and documentation. Has an open mind and attitude. Transparent. Willing to admit and learn from mistakes.
Works well with others in a team environment.
Automating workflows in a distributed compute environment.
Capable of independently driving tasks and activities to completion in an organized and timely manner with excellent quality.
ACADEMIC CREDENTIALS:
Major in EE, CS or related, Master's Degree with 3+ years or Bachelor's with 5+ years working experiences.
LOCATION:
Penang, Malaysia#J-18808-Ljbffr