Job DescriptionAbout the Technology Development and Design Enablement Groups:Technology Development (TD) is the heart and soul of Moore's Law at Intel, enabling Intel to create world-changing technology that enriches the lives of every person on earth. TD drives breakthrough research and develops next generation process and packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona. The Design Enablement (DE) team in TD works closely with the technology team to maximize the value proposition of the technology for our customers thru Design Technology Co-Optimization (DTCO), delivers the Process Design Kits (PDKs) and foundational IPs (FIPs), and carries out technology lead vehicle execution for Si validation. Enablement and optimization of EDA reference flow and design flow on Intel technology play a crucial role in accomplishing DE's charter.As AMS Design Flow engineer, your responsibilities include although not limited to:Operates as a proficient technical contributor specialized in Design Automation and Methodology in the domain of Custom Design Enablement.Assumes leadership roles, entailing the formulation of advanced node Custom Design Reference flow, spanning from conceptualization to the implementation phase, with strong support of industry EDA tools and workflows.Interface with EDA vendors in facilitating best in class design tool enablement, bug resolution, features enhancement requests for future advanced process nodes.Engages in enhancing Custom Layout EDA construction capabilities, encompassing Process Design Kits (PDK), standard cells, Parametric cells (Pcells), Fill Flow, PV runset/rule deck, job submitter development and efficiency optimizations. #DesignEnablementQualificationsBachelor/Master of Science Degree in Computer Science, Computer Engineering, Electronic Engineering, or equivalent.Demonstrate a minimum of 4 years in Physical Design (Custom or ASIC) or Design Automation.Exhibit proficiency in utilizing industry-standard CAD layout tools such as Cadence (Virtuoso), Synopsys (Custom Compiler).Display competence in Physical Verification (DRC, LVS, and others) employing tools like Synopsys ICV or Siemens Calibre SVRF/TVF/PERC coding.Showcase proven expertise in standard cell layout for APR, custom standard cell library, PDK content creation, and the formulation of runset regression test cases- Possess a robust understanding of analog design principles and layout guidelines.Experience in Perl, Python, SKILL, TCL, Shell scripting language. Possess knowledge of advanced technology nodes below 10nm. #designenablementInside this Business GroupAs the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.Posting StatementAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.Working ModelThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
