We represent the Intel Malaysia Client Engineering Group (CEG), where we specialize in the Design and Development (D&D) of Intel Microprocessors (CPUs), System-on-Chip (SoC) solutions, and the latest Neural Processing Unit (NPU) designed to supercharge A.I.
and Machine Learning (ML) tasks.
Currently seeking dedicated and tech-savvy students who are enthusiastic about staying at the forefront of technology to become a part of our extended Part-Time Internship (PTI) initiative.
In this position, you will be involved in the training, design and development of next generation SOC/CPU for a wide range of Intel products and Internet of Things.Your responsibilities will include one or some of the following but not limited to:
Assist design unit owner in Register Transfer Level (RTL) model functional validation.
Use CAD tools extensively to simulate logic behavior and circuit performance and direct physical design for next generation, deep sub-micron embedded circuit solutions.
Verify the circuit behavior against the original simulation model and first silicon.
Define VLSI Structural Design methodology and develop design flows.
Implement structural physical designs, such as synthesis, floor planning, power-grid and clock tree designs, timing budgeting and closure, place and route, RC-extraction and integration.
Verify structural physical designs, such as functional equivalency, timing/performance, noise, layout design rules, reliability and power.
Develop Analog IP on next generation deep submicron process for Intel's SOC, performing tasks related to Very-large-scale integration (VLSI) complementary metal-oxide-semiconductor (CMOS) IC design, solid state physics and physical layout.
Tasks may include circuit design of high speed clocking related circuits (phase-locked loop (PLL), delay-locked loop (DLL), bandgap) or high voltage input/output (IO) (double data rate (DDR)/LPDDR, General-purpose input/output (GPIO), OPIO).
Responsible for integration of third-party IPs -- synthesis, functional and/or timing convergence, and pre and post-silicon debug of IPs developed by various external vendors as well as within the company.
Handle signals crossing power planes and clock domains, industry standard protocols including hardware and software details dealing with Memory LPDDR, storage eMMC, SATA, UFS, peripherals PCIe, USB, and MIPI interfaces in SOC devices.
System integration dealing with Si/Platform/FW/MW/drivers/OS/Apps on Android and Windows-based tablets and phones.
Validate and integrate third party IPs ensuring they meet product specifications and functionality before they are productized into physical chips.
Work closely with design teams and architects to implement the low-level RTL design to ensure overall good functionality of the chip.
Develop specific test environment/platform, validation methodology and test plan to validate SOC design by identifying and exercising boundary conditions and special cases to break the chip and find that last elusive bug.
Oversee definition, design, verification, and documentation for SoC System on a Chip development.
Determine architecture design, logic design, and system simulation.
Define module interfaces/formats for simulation.
Perform Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs.
Contribute to the development of multidimensional designs involving the layout of complex integrated circuits.
Perform all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
Analyze equipment to establish operation infrastructure, conduct experimental tests, and evaluate results.
May also review vendor capability to support development.
Qualifications:
Open to Year 1, Year 2 and Year 3 students
Possess a minimum of Bachelor's in Electrical and/or Electronic Engineering/Computer Engineering/Microelectronics/Mechatronic, or related Electrical Scientific STEM field.
Proficient in programming; C++/Unix/VLSI/Verilog/Circuit Design knowledge will be an added advantage.
CGPA: 3.67 and above or equivalent
Duration: minimum 1-year internship contract
Location: Flexibility to be on-site in Penang and work remotely.#J-18808-Ljbffr