Design Verification Engineer

Design Verification Engineer
Location:Penang (hybrid model)
What you will do:
Digital function verification for power management and signal processing IC products.
Verification plan development according to product definitions and architecture.
Verification environment development with SystemVerilog and UVM.
Test case collection, regression management, verification progress updates.
Verification flow improvement on both module level and top level.
Verification IP introduction and development.
Analog behavior modeling support for system function verification.
Writing technical documentations.
What you will need:
BS degree with 8+ years or MS degree with 5+ years experience in digital verification.
Excellent SystemVerilog coding skills.
Hands-on experience of building verification environment using SystemVerilog and UVM.
Hands-on experience of verification management is a strong plus.
Strong problem-solving skills.
Experienced with either Cadence or Synopsys EDA tools.
Excellent communication and teamwork skills.
Why work for us?
Competitive compensation and benefits: competitive salaries, bonuses, and benefits packages including health insurance, retirement plans, and paid time off.
Career development opportunities: various training programs, mentoring, and leadership development programs.
Work-life balance: flexible work arrangements, including work-from-home options.
Employee engagement initiatives: team-building activities, social events, and employee recognition programs.
Health and wellness programs: various on-site programs to help employees maintain a healthy work-life balance.
Nexperia is an Equal Opportunity/Affirmative Action Employer.#J-18808-Ljbffr