Design Verification Engineer

We are hiring Senior Staff / Staff Verification Engineer for IP / SoCJob Description:Responsible for SoC's IP level and full chip level verification.Develop verification plan for complex digital IP from design spec, work closely with design engineers to identify important verification scenarios.Create verification environment/testbench with Bus Functional Model (BFM) using SystemVerilog, UVM, C.Identify and implement functional coverage and SystemVerilog Assertions to catch functional bugs and to boost design quality prior to tape-out.Develop directed/use case/random test cases using SystemVerilog and C, analyse test results, debug tests and improve verification quality.Knowing to use Formal verification with SystemVerilog Assertion (SVA) to verify IP block is a plus.Requirements:Bachelor/Master Degree in Electrical & Electronics/Computer Engineering or equivalent.Familiar with AMBA bus protocol (AXI, CHI, ACE, APB).Experience with verification methodology such as SystemVerilog, OVM, UVM, C.Experience with functional coverage/SVA assertions and test sequence/case writing using C and UVM sequence.Experience with the full verification execution cycle.Experience in developing measurable verification plan.Experience with function verification for common SoC building blocks and verification IP for PCIe/USB/ UFS/ Memory Controller, etc. are added advantages.Strong problem solver, communicator and team player.Scripting skills in Perl, Python, TCL, shell, etc. 8 years' experience in Design Verifcation.