Design Verification Engineer

Job Description: Will be part of a team that handles Verification for complex IP's and close the Verification to the challenging milestones.IP Verification: VR creation as per the chip requirements and UVM/OVM Test benches creationSupport in building verification infrastructure at the chip level as per the requirementsCapable of handling multiple areas of IP Verification: RTL, Power Aware and Gate Level VerificationWorking with the team and functional leads; Some interaction with cross functional groupsJob Requirements:  Have experience of digital IP verification with SV/UVM/Formal Verification or new methodology of the industryGood understanding of ASIC verification concepts and techniques and Verilog/System Verilog and UVMIt's a plus to be good at some script language, such as Perl, python. Or some database experience (for IP technical info maintain).It's also a plus if have over 3 years' experience focusing on SV assertion/coverage/formal verification.Bachelor's degree or higher in Electrical and Electronics Engineering or related fieldFresh graduate are welcome to apply