Job Description This team develops next Generation PCI Express, DMI and CXL to lead the industry. Responsibilities include ( but not limited to)
Performs Functional Verification/Formal verification of IP logic to ensure design will meet specification requirements. Develops System Verilog (SV) Testbench and building RTL models in OVM/UVM environment. Develops Verification Plans base on microarchitecture specifications and drives technical reviews of plans. Executes verification plans in PSV environment to verify the design and uncover bugs. Develops tests content (SV, OVM/UVM), System Verilog Coverage Points & Assertions, debugging regressions involving Verification Testbench components (testbench modeling, environment, BFM, scoreboard, DUT, checkers/trackers/interactive debug) Ability to drive Validation Strategies to deliver predictable QoV (quality of validation) Participates in the definition of verification infrastructure for functional design verification. Develops automated tools and scripts for pre-silicon validation environment.
Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
The applicant should have a Bachelor degree in (Electrical and Electronics or Computer or equivalent) Engineering or higher.
Experience in SystemVerilog, OVM, UVM, RTL model build or testbench development. Experience in Logic Design, ASIC Design & Verification, FPGA Design & Verification Capable of developing test plans, test contents and coverage points for verification purpose based on high-level architecture specification. Experience in PCI Express or any standard bus protocol would be added value. Familiarity or experience in RTL design with Verilog and/or VHDL is a strong plus Good programming skill in Perl, C++ and shell scripts Good analyzing and debugging skills, and creative in problem-solving. Good communication skill. Highly motivated to learn and adapt to fast-evolving technologies and environments. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. #J-18808-Ljbffr
