WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance.THE ROLE:
As a member of the Central Engineering Group, you will help bring to life cutting-edge designs. The focus of this role is to plan, build, and execute the verification of new and existing features for High Speed IO Protocol IPs (USB, PCIe, Ethernet, UFS) that is used in AMD's product portfolio resulting in no bugs in the final design.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
Able to work well inside team/cross functional team.
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
Build the directed and random verification test and any required changes to the test environment.
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.
PREFERRED EXPERIENCE:
Experience in IP level ASIC verification.
Experience in debugging RTL code using simulation tools.
Experience in using UVM testbenches and working in Linux and Windows environments.
Good understanding of UVM, Verilog, System Verilog, C, and C++.
USB, UFS, Ethernet, PCIe, AXI knowledge is a plus.
Good understanding and hands-on experience in the UVM concepts and SystemVerilog language (SVA, UVM scoreboard).
Good working knowledge of functional coverage and code coverage closure.
Scripting language experience: Perl, Ruby, Makefile, shell preferred.
Over 3 years of digital IP verification with SV/UVM/formal verification or new methodology of the industry.
ACADEMIC CREDENTIALS:
Bachelors or Masters degree in computer engineering/Electrical Engineering.
LOCATION:
Penang, Malaysia#J-18808-Ljbffr