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THE ROLE:
This is a lead engineering position responsible for electrical validation of Datacenter Server SoC Post-Silicon IO interface, in a way that is end to end customer focused, innovative, efficient and drives highest quality standards. It requires both pre and post Si engagement and close collaborations within and outside the team to ensure design and test content robustness, ultimately delivering highest quality products to customers.
THE PERSON:
The ideal candidate will be capable of communicating problems, solutions, and project status up to the executive level. You will provide technical supervision or mentoring to junior engineers and influence others as a technical leader. You have the capability assuming the consultative or leadership responsibilities for large projects or product development initiatives, while dealing with internal and external groups on behalf of the group or project. This role allows the opportunity to influence technical decisions that have a significant impact on multiple products or the product line.
KEY RESPONSIBILITIES:
Define and develop IO electrical validation requirements and electrical test coverages to guarantee compliance and success of the Server SoC devices at platform level.
Develop IO electrical validation strategies plans and schedules by integrating different requirements from various engineering and business departments.
Driving exploration of IO electrical validation methodology platform and infrastructure enablement to improve process and throughput.
Collaborate, review and influence design teams including hardware/packaging/board/platform during Pre-Si stage to ensure Pre-Si IO electrical simulation quality adhere to spec, to develop reference platform and to ensure validation hooks and dft availability.
Hands-on measurement and characterization of Post-Si IO electrical interfaces performance using hardware lab equipment such as oscilloscopes, TDR, VNA, logic analyzer, BERTScope, probing stations and etc.
Own, drive and debug Post-Si electrical bugs and performance marginality with hardware/BIOS/Firmware/Operating System implementations and recommends solutions.
Support system and tester level validation teams to identify and close analog and electrical issues.
Analysis and disposition of early customer returns to drive understanding of design marginalities or develop test content to screen these units where needed.
As part of a highly technical team, you will have the opportunity to innovate on and establish new test methodology, as well as new test development process improvements. Drive test optimizations to reduce test cost, enhance product quality, improve efficiency and accelerate stability.
PREFERRED EXPERIENCE:
Experience with Signal Integrity and/or Power Integrity.
Experience with any of the following: DDR4/5, LPDDR4/5, RDIMM JEDEC standard, PCIe Gen4/5/6, Analog Power Management Characterization.
ACADEMIC CREDENTIALS:
Bachelors or Master's in computer engineering, computer science, electrical engineering, or comparable disciplines.
LOCATION:
Penang, Malaysia
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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.#J-18808-Ljbffr