Smts Systems Design Engineer - Server Platform Emulation Validation

Details of the offer

WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
THE ROLE:
AMD is looking for a highly talented engineer to join our Server Platform Solution Engineering (SPSE) team as a senior member of technical staff working on server platform emulation validation for next-generation AMD EPYC systems.
As a server platform emulation validation engineer, we are shift-left testing strategist specializing in AMD EPYC system testing. The focus of this role is to plan, build, and execute the verification of new and existing features for next-generation AMD EPYC systems.
THE PERSON:
You have a passion for modern, complex server architecture verification who thrives in an environment that requires creative debugging skills, drive to improve pre-silicon system validation coverage capabilities, and a passion for improving the overall shift-left strategies and goals. You are a team player with excellent communication skills, responsible and willing to learn new skills. You have strong analytical and problem-solving skills and are ready to take on challenges.
KEY RESPONSIBILITIES:
Responsible for validation of firmware stack, BIOS, OS, DFX, debug tools on pre-silicon emulation platforms.
Develop test plans and identify design and firmware dependencies to ensure smooth execution of test plans.
Write directed tests to verify features in a co-simulated and emulated/FPGA hardware environment.
Debug SOC level failures and collaborate with SOC design and firmware teams to complete feature validation.
Write monitors and checkers to support end-to-end firmware/hardware validation.
Run emulator workloads to test new features.
PREFERRED EXPERIENCE:
Good communication skills.
Experience with FPGA and/or emulation platforms.
Experience in developing System Verilog based test content.
Experience in developing C++, Python, Perl, Ruby, Shell, and TCL test content.
Experience in validating hardware features for at least 2 or more projects in a pre-silicon environment.
Experience in debugging failures using waveform viewers, log files, and microcode trace dumps.
Knowledge of one or more protocols: SPI, DDR, SATA, USB, AXI, PCI, PCIe, MIPI, WLAN, I2C/I3C, CXL.
ACADEMIC CREDENTIALS:
Bachelor's or Master's in electrical engineering, computer engineering, or comparable disciplines.
LOCATION:
Penang, Malaysia
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Nominal Salary: To be agreed

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