Job Description Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure highquality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Education: MTech/BTech in Electrical Engineering or Computer Science.
Experience: 3-7 years in ASIC design.
Skills:
- Proficient in System Verilog/Verilog RTL coding.
- Expertise in power-aware RTL coding/design.
- Ability to understand the micro-architecture of CPU subsystems and design associated component IPs, as well as define technical proposals.
- Sound exposure to front-end flows such as Lint, CDC, low-power checks, etc.
- Experience with synthesis, DFT, FV, and STA.
- Familiarity with protocols like AHB, AXI, ACE, and CHI is desirable.
- Hands-on experience in multi-clock designs and asynchronous interfaces.
- Advanced knowledge of low-power techniques and tools such as UPF/CPF and CLP.
- Good understanding of constraint development for physical design implementation and static timing analysis.
- Excellent communication skills and ability to work with global teams.
Inside this Business Group The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential. Other Locations MY, Penang Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel's offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at and not fall prey to unscrupulous elements. Working Model This role will require an on-site presence. #J-18808-Ljbffr
