Job DescriptionDevelops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block.Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.QualificationsWe are looking for B. Eng or M. Eng in Electronics, Computer or Electrical Engineering graduates who have 5+ years of digital design exposure and experience.Job working experience in verification and integration activities including but not limited to test plan development, test writing, debug, integration and familiarity with verification methodologies such as OVM, UVM or VMM.Enjoy picking up protocol knowledge in I/O specifications such as USB2, USB3, SATA, PCIe.Best match if you have knowledge in HVM, DFX, scan, JTAG and debug functionality.Genuine curiosity into microprocessors, computer system architecture and high speed design as well as producer-consumer transactions.Dedicated and proficient in digital state machine architecture and logic design.Working level mastery of Unix based design environment, industry standard digital design tools, scripting languages and ASIC flows.BenefitsWe offer a total compensation package that ranks among the best in the industry.
It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefitshere.
Working ModelThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
* Job posting details (such as work model, location or time type) are subject to change.#J-18808-Ljbffr