Soc Physical Design Engineer

THE ROLE: Physical design including block level place/cts/route, full chip floor planning, timing closure, physical verification etc.THE PERSON: Always be positive, dedicated and good team playerGood listening, writing, and speaking EnglishGood communication skillsKEY RESPONSIBILITIES: Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation.Focus on physical design of deep sub-micron GPU chips including block level, full chip floor planning, timing closure, place and route, physical verification etc.The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.PREFERRED EXPERIENCE: Tape-out experience in deep submicron processKnowledgeable in all aspects of ASIC design flowDemonstrate strong leadership and work well with cross-functional teamsDemonstrate strong leadership, work well with cross-functional teamsFamiliar with Unix/Linux environmentFamiliar with Back-End (physical design) EDA toolsFamiliar with Front-End EDA toolsGood at scripts, like Python/perl/Tcl/shellACADEMIC CREDENTIALS: MSEE / Microelectronic preferredMSEE with 3+ years or Bachelor with 5+ years of industrial experience in ASIC design.LOCATION: Penang, Malaysia
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