In your new role you will:
Implement the physical layout of circuit based on schematics provided by circuit design engineers.
Check the correctness of layout using DRC/LVS tools (Calibre).
Work with circuit design engineers in the evaluation of various circuit options and their impact on layout, and determine the optimized approach.
Carry out LODR0-2 checking process to ensure the database is clean and prepare all necessary documents in order to perform IPS3/IPV.
Plan, schedule, and coordinate sub-cell layout.
Liaise with CAD team/CAD tool vendor to solve problems/issues encountered with layout tools.
Involve in layout productivity & quality enhancement projects and contribute in CI conference related activities.
Assist in liaising with cross-functional team leader in project-related matters.
Involve in scripting for layout improvement ideas.
You are best equipped for this task if you have:
Bachelor's Degree in Electrical/Electronic Engineering/Physics with VLSI exposure or equivalent.
6 to 9 years of job experience in layout design field is preferred.
Hands-on experience in analog layout from scratch, implementation of analog layout techniques, IR drop/EM analysis.
Deep understanding of analog circuit layout concepts in submicron CMOS technologies.
Strong technical, analytical & problem-solving skills in layout design.
Ability to work as a strong team player and participate in cross-functional activities.
Good interpersonal, verbal and communication skills with good initiative at work.
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