Staff Soc Dft Design Engineer

Details of the offer

Electrical/Electronic Engineering (Engineering)
Job Type:Full time
Job Description:
Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block.Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.Qualifications:
Minimum qualifications are required to be initially considered for this position.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Bachelor/Master of Engineering or Science degree in Electronic, Electrical or Computer EngineeringAt least 5 years of professional experience in related field of workPreferred Qualifications:
Strong technical knowledge in Design-for-X (DFx), where X is Test (DFT), Debug (DFD), Manufacturing (DFM) or Validation (DFV)Hands-on experience in using the DFT industrial tools for Memory-BIST and/or Scan Design for RTL design, integration and verificationFamiliar with the manufacturing testing for wafer sort and package, with good experience in driving resolution to post-Silicon test issuesAbility to assume ownership, drive discussions with stakeholders, including cross-site partners to achieve resultsPassionate to continuously learn and develop the technical and leadership skills to drive technical leadership for the teamRequirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.Work Model for this Role:This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.#J-18808-Ljbffr


Nominal Salary: To be agreed

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