Usb Ip Design Verification Engineer

Details of the offer

Job DescriptionPassionate IP design Verification Engineer who is motivated to work on fast moving USB IP development across various Client products. The experienced engineer will have an opportunity to define a robust and high-quality test coverage plan to validate new generations of USB IP and challenging new architectural features. The responsibilities cover:
Scoping and development of validation test plans for new architectural features and next generations USB IP development.
Developing test contents, coverage points and assertion checks.
Developing testbench infrastructure (monitors, scoreboards/checks, BFMs, etc) to close on validation coverage.
Finding and implementing correct measure for failing tests.
Continue to strive for innovation in problem-solving to improve test coverage in efforts to minimize project execution time while increasing efficiency.
Understanding SoC/Subsystem validation environment, and providing IP validation support.
QualificationsThe applicant should have a Bachelor degree in Electrical and Electronics or Computer or equivalent Engineering or higher.
Familiarity or experience in RTL design verification with System Verilog.
Knowledge in any high speed IO IPs, such as USB or PCIe is a strong plus.
Good analyzing and debug skills, and creative in problem-solving.
Strong skills in communication, initiative, innovation and collaboration in a diverse team.
Positive energy and highly motivated to learn and adapt to fast-evolving IP technologies and environments.
BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefitshere.
Working ModelThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
* Job posting details (such as work model, location or time type) are subject to change.
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Nominal Salary: To be agreed

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