Graduate Talent Program - Design Enablement Team In Technology Development Group

Details of the offer

Technology Development and Design Enablement Groups is looking for fresh talent like you!  We are at the core of innovation at Intel, driving cutting-edge research and developing the next generation of process and packaging technologies, the DE team within TD works closely with the technology team to ensure our technology meets the needs of our customers. DE provides essential design kits (PDKs), foundational IPs, and supports the design process to validate and optimize our technology. The team also focuses on improving design flows and tools to enhance the overall design process on Intel's technology.
Explore our open roles and take the next step in shaping the future with us, driving the creation of industry-leading products. Your journey to innovation starts here!
Roles and responsibilities varies depending on the role you are being assigned to: - Design EnablementYou will work on creating and optimizing design flows built on Intel's reference flow and external EDA tools. This comprehensive design flow covers both front-end and back-end processes, from RTL to GDS, including digital and analog design, verification, and signoff. Additionally, you'll apply AI/ML and data analytics techniques to tackle complex design challenges.
DTCO APRAs a Design Technology Co-Optimization (DTCO APR) Engineer, your role involves supporting RTL synthesis and place-and-route experiments to enhance product power, performance, and area across current and future process nodes. You'll manage floorplan changes, predict scaling impacts, improve cell utilization, and optimize power, performance, and congestion metrics using advanced tools and methodologies.
Memory DesignYou will focus on pathfinding and development of advanced memory technology and circuits to enable best-in-class memory collateral/IP and product design across all generations of Intel process technology.
PDK QAA PDK is a collection of artifacts that represents Intel's semiconductor process and is used by product designers to model, implement and verify Intel's mobile, desktop and server products before it is manufactured. You will validate PDK quality across process nodes and EDA flows, develop and execute regression test suites, create custom layout and analog circuit designs, and debug issues in pre- and post-layout simulations.
PDK DevelopmentThe job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors, and product design teams to develop and deliver high quality technology collaterals, models, and enablement of EDA tools.
Standard Cell Library Design Automation EngineerIn this position, you will participate in design, development, QA and delivery of corporate standard cell libraries using leading process technologies for use in design of Intel's next-generation SoCs and microprocessors.
Requirements:  Possess a minimum of Bachelor/ Master in Electrical and/or Electronic Engineering, Computer Engineering, Computer Science, or other related Electrical Scientific STEM field.CGPA: 3.7 and above or equivalent. Ability to work in a fast-paced, collaborative, and often intense project schedule.Unix/ Linux/ VLSI/ EDA tools knowledge will be added advantage.Strong interest/proficiency in either of these field: digital circuit design/circuit simulation/ synthesis/ place and route/ physical design verification/scripting Proficient in Scripting Language - TCL, Perl, Python, cshell. Candidates must be willing to relocate to Penang for a hybrid work arrangement.Candidates should be open to a contract-based Graduate Talent role.


Nominal Salary: To be agreed

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